1. Field of the Invention
The present invention relates to a processor, and more particularly, to a method for a processor to access an external memory.
2. Description of the Prior Art
When a processor is operating, a plurality of internal circuitry modules reads data from or writes data to a Dynamic Random-Access Memory (DRAM). These circuitry modules send a plurality of read/write commands into a DRAM controller to request executing the operation of reading/writing the DRAM.
When the processor sends these read/write commands to the DRAM controller, it does not supply any DRAM-aware protocol scheduling for these read/write commands at the processor-end. Therefore, the burden of the back-end DRAM controller is increased, the efficiency for accessing data is lower, and a response time is longer.